1 Field of the Invention
This present invention relates to the area of memory card connection and optimization of the use of mainboard area. The invention relates more particularly to a interface connection device used to connect a mainboard to a memory card of the type housing two series of memory modules. In what follows, mainboard refers to any board having at least one processor and intended to be connected to one or more other cards (secondary cards) or indeed to memories. For example, the mainboard can be a motherboard of a CPU.
The use of memory modules of the DIMM type (dual in line memory module) in computer equipment is known. These memory modules generally take the form of 64-bit memory barrettes, equipped with 84 connecting pins on each side, making 168 DTRS in all. A “daisy chain” type bus topology is often used to establish the connection between the memory modules, in particular between modules of the FBD type (fully-buffered DIMMs; JEDEC JC-45.4). The expression “daisy chain” is used to indicate a method of connection between modules or between machines which use a single logic line to connect the modules to each other; with the bus being terminated at each end by a terminator, and only one module is able to emit at a time.
The FBD modules are connected continuously in a “daisy chain” on an FB-DIMM channel. It is possible to put up to 8 DIMM modules on any one channel. It is also beneficial to use the channels in pairs, for several reasons including the following:
to increase the accessible memory capacity, so that one sometimes accesses one channel and sometimes the other according to the memory zone targeted, so that it is possible to exceed 8 barrettes. Although there is no categorical imperative here in this regard, performance or availability considerations favour configurations where the barrettes are divided equitably between the 2 channels;
to increase the memory speed and to be able to launch memory access to one channel while one is launching another on the other channel. In this case, there will generally be the same number of barrettes on each channel so as to balance the load between the 2 channels, thereby extracting the best performance. A conventional use of this arrangement is memory interlacing, which is used to execute memory accesses in rapid succession to successive addresses. The even addresses are then served by one channel and the odd addresses by the other (in this case, the 2 channels are necessarily connected to an identical number of barrettes, since it would make no sense to have only even (or odd) addresses in one given memory zone);
to increase the width (number of bits) of the memory word accessible in a single operation from the FB-DIMM barrettes (the 2 channels, used simultaneously, then give one word which is twice as wide). In this case, the 2 channels must necessarily be put in relation with an identical number of barrettes; otherwise one part of the memory would be composed of incomplete memory words.
It is therefore observed that very often, in the case of two channels, these will be made up from the same number of memory barrettes, and that the composition of the memory configuration takes the form of a progressive and simultaneous accretion of the two channels. However, allowing for this additional constraint creates a certain number of difficulties. In fact, whatever the number of memory barrettes specified as a maximum and finally installed on each channel, the following technical problems arise in a computer unit:
accessibility of the memories; the FB-DIMMs are of the “hot plug” type (capable of being connected or disconnected without switching off the remainder of the system), and it is possible to add memory barrettes beginning with slot 1 up to slot 8. It is likewise possible to remove them, beginning at the end of the “daisy chain”;
optimisation of the CPU board area. With a connector having a length of 155 mm and a pitch of 10.5 mm (0.41 inches), the memories are quite bulky and, for example, 16 FB-DIMM modules represent a board area of 160×180 mm (in one row) or 320×90 mm (in two rows);
difficulty in making best use of the volume inside the 2U or 3U computer unit (1U is 44.45 mm according to standard EIA-310-D, allowing the referencing and vertical positioning of the computer equipment in a rack of the high-density type in data centres, network rooms and cabling cabinets);
high cost of the cards providing a configuration with many memories;
cooling that requires orientation of the memory barrettes which must be compatible with the flow of air necessary to cool the whole unit.
In existing designs, the FBD type memory modules are placed on the mainboard containing the processor. A disadvantage of this type of arrangement is that the area occupied on the processor board by the FB-DIMMs is very significant. Moreover, compactness is not optimised, since the volume generally available above the mainboard is not used. It should also be noted that, regardless of the number of memory barrettes installed, the cost of the mainboard (printed circuit area+FBD) is that of a configuration with 8 DIMM modules per channel.
Furthermore, since the channels are used in pairs, the simple fact of dividing the memories in two by the use of secondary cards (daughter cards), positioned horizontally or vertically, does not result in both compactness and accessibility to the memory modules. An additional drawback of this type of arrangement is its poor growth flexibility if it is desired to add memory capacity.